1. Field of the Invention
This invention relates to nonvolatile semiconductor memory devices, and more particularly to a flash-type nonvolatile semiconductor memory device that operates with a 5-V power supply only.
2. Description of the Related Art
Recent developments in semiconductor technology allow new products of the fields except the semiconductor fields and help lighten and miniaturize conventional products remarkably, giving extensive changes to our daily life. Above all, semiconductor memory technology, which is closely related to modern society, has been making remarkable advances. Semiconductor memories are broadly classified into volatile memories such as DRAMs whose stored data is lost when power is off and nonvolatile memories whose retained data is not lost even when power ceases.
Nonvolatile memories, widely used as read-only memories, are characterized by retaining the information even when the power ceases. They can be divided into mask ROMs (Read-Only Memories) into which information is written during the manufacture of the elements, PROMs (Programmable ROMs) into which users themselves can write data, UV-EPROMs (Ultraviolet Erasable Programmable ROMs) that allow the information to be erased by ultraviolet radiation, and rewritten into them and EEPROMs (Electrically Erasable Programmable ROMs) that enable electrical erasure of data. Although EEPROMs are the most user-friendly ROMs, they have many technical problems to overcome, such as difficulties in very high integration. Presently, this limits applications of EEPROMs compared with other types of memories.
Today, flash-type semiconductor memories designed for very high integration have been attracting attention and encouraging heated development in many companies of the world. For example, in the 1989 ISSCC (International Solid State Circuit Conference), two U.S. companies Intel and Seeq announced 1M-bit flash memories and already put them on the market.
As shown in FIG. 1, memory cells constituting conventional flash-type semiconductor memories are MOS field-effect transistors with a two-layer gate structure of a floating gate 102 and a control gate 103 both formed above a semiconductor substrate 101. The writing of information can be electrically achieved by injecting hot carriers generated in the vicinity of a drain 104 into the floating gate 102. Hot carriers can be generated by applying a high voltage to the drain 104 and control gate 103 and connecting a source 105 to the ground to accelerate the electrons flowing through the channel by a high electric field generated near the drain 104. To erase the information, a high voltage is applied to the source 105 and the control gate is connected to the ground, so that a high electric field is applied to the thin silicon oxide film 106 between the source 105 and floating gate 102, thereby allowing a tunnel current to flow through the silicon oxide film 106. The memory cell of FIG. 1 is characterized by its very simple structure and the suitability for miniaturization because of the self-aligning formation of each of the floating gate 102, control gate 103, drain 104, and source 105.
With the structure of FIG. 1, however, applying a high voltage to the source 105 for erasure causes a phenomenon known as band-to-band tunneling to take place at the surface of the source 105 below the floating gate 102. As a result of this, in the depletion layer of the source 105, carriers are generated and accelerated by a high electric field. The accelerated carriers cause ionizing collisions, which in turn generate still more carriers, resulting in a very large current flow between the source 105 and substrate 101. That is, the substrate current is considerably large compared with the tunnel current flowing through the silicon oxide film 106. Thus, the supply of erasure high voltage V.sub.pp (e.g., 12.5 V) from a high voltage generator circuit formed on the chip requires the circuit to have a large power capacity, making the chip size very large. On the other hand, externally supplying the erasure high voltage V.sub.PP goes against the concept of operating a flash-type EEPROM with a single power supply (5 V).
To avoid the above problems, a method has been proposed in which a cell region is formed in a p-well 202 formed in a n-type semiconductor substrate 201 as shown in FIG. 2. With this arrangement, the erasing of information is performed by applying a high voltage V.sub.PP to the n-type silicon substrate 201, p-well 202, source 203, and drain 204, connecting the control gate 205 to the ground, and allowing a tunnel current to flow through the thin gate oxide film 206. In this case, no high voltage applied across the source 203 and p-well 202 results in a decrease in the substrate current caused by the aforementioned band-to-band tunneling, allowing the flash-type EEPROM to operate with a single power supply.
For EEPROMs composed of memory cells having the structure shown in FIG. 2, however, rewriting data in blocks instead of overall erasure requires providing one well for each block. This makes it necessary to have isolating regions between wells, which increases the chip size substantially when the number of block divisions is extremely large, making them unsuitable for practical uses.